Paper Info
Title
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.
Abstract
Because of the expansion of high performance computing (HPC) and server market, demand for HBM DRAM is increasing. With this market flow, diverse customers require various HBM product families. One customer requirement is full bandwidth with less density. Therefore, this work presents a HBM DRAM, which supports 4, 8, and even 2-hi stacks with full-bandwidth performance. The HBM DRAM adopts a peripheral base die architecture, which has smaller chip size and good testability resulting in more manufacturability. This architecture can compensate for process variation, since this problem among core dies within the same known good stacked die (KGSD) is the key issue of TSV-based stacked DRAM [1]. Layout aligning between PHY and TSVs improves the speed performance of the whole system due to reduced data skew. The peripheral base die contains address/command decoders (COMDEC), a core pipe-out (POUT) signal generator, and internal power, references and bias generators. A small-swing technique on a heavy load interface can reduce dynamic power and also has tolerance to process variations.
Year
Venue
Field
2016
ISSCC
Dram,Testability,Supercomputer,Computer science,Electronic engineering,Dynamic demand,Bandwidth (signal processing),Process variation,Skew,Design for manufacturability,Embedded system
DocType
Citations 
PageRank 
Conference
2
0.47
References 
Authors
2
22
Name
Order
Citations
PageRank
Jong Chern Lee120.47
Jihwan Kim2173.64
Kyung Whan Kim3856.11
Young Jun Ku421.14
Dae Suk Kim520.80
Chun-Seok Jeong6194.20
Tae Sik Yun721.14
Hong-Jung Kim8213.70
Ho Sung Cho921.48
Yeon Ok Kim1020.47
Jae Hwan Kim11152.07
Jin-Ho Kim1246944.48
Sangmuk Oh1321.48
Hyun Sung Lee1420.80
ki hun kwon15502.88
Dong Beom Lee1620.80
Young Jae Choi1720.80
Jeajin Lee1820.47
Hyeon Gon Kim1931.17
Jun Hyun Chun20395.17
Jonghoon Oh2141.87
Seok Hee Lee2221.14