| 23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications. | 0 | 0.34 | 2017 |
| 23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. | 1 | 0.37 | 2017 |
| 18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. | 2 | 0.47 | 2016 |
| High Bandwidth Memory(Hbm) With Tsv Technique | 0 | 0.34 | 2016 |
| 18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme. | 1 | 0.37 | 2016 |
