Name
Title | ||
|---|---|---|
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS |
Abstract | ||
|---|---|---|
With recent advancements in SoC integration, modern SoC architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between -226dB and -234dB from 0.8GHz to 5GHz is presented. The PLL features a modular implementation and therefore could be used as the local clock source or as part of a clock-generation hub. The hub provides reference clocks to subsystems from a single platform crystal oscillator through a combination of divisions and distributions. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7418041 | International Solid-State Circuits Conference |
Field | DocType | ISBN |
Power budget,Phase-locked loop,Computer science,Crystal oscillator,Electronic engineering,CMOS,Bandwidth (signal processing),Jitter,Modular design,Electrical engineering,Bandwidth management | Conference | 978-1-4673-9466-6 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuan-Yueh James Shen | 1 | 2 | 1.05 |
| Syed Feruz Syed Farooq | 2 | 2 | 1.05 |
| Yongping Fan | 3 | 3 | 2.09 |
| Khoa Minh Nguyen | 4 | 9 | 1.63 |
| qi wang | 5 | 38 | 7.25 |
| Amr Elshazly | 6 | 242 | 28.08 |
| Nasser A. Kurd | 7 | 115 | 13.54 |