Paper Info
Title
18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme.
Abstract
The emergence of the internet of everything (IoE) demands high-performance, real-time multi-media and wideband networking in battery-operated mobile systems. For this reason, higher bandwidth and lower power mobile DRAMs are becoming increasingly critical. As promising candidates of next-generation mobile DRAM, the development of LPDDR4 [1] and wide-IO2 (WIO2) DRAM is ongoing these days. The conventional single data rate (SDR) wide IO DRAM [2] has achieved ×4 data bandwidth compared to LPDDR2 by increasing the number of IOs (e.g. 512 DQs). The WIO2 DRAM in this paper has 512 DQs, which is the same as SDR wide-IO DRAM, but by using double data rate (DDR) and operating at 1066Mb/s, its bandwidth achieves 68.2GB/s, which is quadrupled compared to LPDDR4 (single-die comparison). Moreover, since WIO2 DRAM is stacked in a 3D structure with the DRAM controller (system-in-package type), the input/output capacitance (CIO) is decreased and a power efficiency of 28mW/GB/s in READ operation mode is achieved.
Year
Venue
Field
2016
ISSCC
Dram,Wideband,Computer science,Universal memory,Electronic engineering,Input/output,Bandwidth (signal processing),Electrical engineering,Double data rate,CAS latency,Memory rank,Embedded system
DocType
Citations 
PageRank 
Conference
1
0.37
References 
Authors
4
19
Name
Order
Citations
PageRank
Young Jun Yoon111.04
Byung Deuk Jeon210.37
Byung Soo Kim311712.78
Ki Up Kim410.37
Tae Yong Lee510.37
Nohhyup Kwak610.70
Woo Yeol Shin710.37
Na Yeon Kim850.79
Yunseok Hong910.37
Kyeong Pil Kang1010.37
Dong Yoon Ka1110.37
Seong Ju Lee1210.37
Yongsun Kim13333.92
Young Kyu Noh1410.37
Jae-Hoon Kim1526865.73
Dong Keum Kang1610.37
Ho Uk Song1710.37
Hyeon Gon Kim1831.17
Jonghoon Oh1941.87