Name
Abstract | ||
|---|---|---|
With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7417908 | 2016 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
NRZ-electrical serial-link transceiver,CMOS,data traffic,data center,wireline chip-to-module,chip-to-chip communication,power efficiency,receiver front-end,baud-rate architecture,bit rate 56 Gbit/s,size 28 nm | Electrical efficiency,Serial communication,Transmitter,Wireline,Clock recovery,Transceiver,Computer science,Electronic engineering,CMOS,Electrical engineering,Detector | Conference |
ISBN | Citations | PageRank |
978-1-4673-9466-6 | 10 | 1.14 |
References | Authors | |
3 | 17 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takayuki Shibasaki | 1 | 66 | 12.00 |
| Takumi Danjo | 2 | 12 | 2.35 |
| Yuuki Ogata | 3 | 15 | 3.01 |
| yasufumi sakai | 4 | 14 | 3.57 |
| Hiroki Miyaoka | 5 | 13 | 2.68 |
| futoshi terasawa | 6 | 11 | 2.14 |
| Masahiro Kudo | 7 | 41 | 7.70 |
| Hideki Kano | 8 | 20 | 2.84 |
| Atsushi Matsuda | 9 | 12 | 3.50 |
| Shigeaki Kawai | 10 | 22 | 3.87 |
| Tomoyuki Arai | 11 | 14 | 3.95 |
| hirohito higashi | 12 | 11 | 2.14 |
| naoaki naka | 13 | 11 | 2.14 |
| Hisakatsu Yamaguchi | 14 | 64 | 10.20 |
| Toshihiko Mori | 15 | 20 | 6.30 |
| Yoichi Koyanagi | 16 | 68 | 13.60 |
| Hirotaka Tamura | 17 | 204 | 32.19 |