Paper Info
Title
On-chip Sparse Learning with Resistive Cross-point Array Architecture
Abstract
Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing. However, even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation. In this paper, the resistive cross-point array architecture (CPA) is proposed to achieve on-chip acceleration of sparse coding, especially the matrix/vector operations that are intensively used in the algorithm. Learning and recognition experiments are conducted with the MNIST handwriting dataset. By co-optimizing the algorithm, architecture, circuit, and resistive synaptic devices, SPICE simulation at 65nm demonstrates that the CPA is able to accelerate sparse coding computation by more than 3800X, compared to software running on an 8-core CPU. Furthermore, this work investigates the technological limitations of a realistic resistive CPA, including reduced ON/OFF range of synaptic devices, nonlinearity in programming, spatial and temporal variations, and interconnect parasitics. The results illustrate both enormous opportunities and practical barriers of resistive CPA in real-time learning on a chip.
Year
DOI
Venue
2015
10.1145/2742060.2743757
ACM Great Lakes Symposium on VLSI
Field
DocType
Citations 
MNIST database,Computer science,Resistive touchscreen,Neural coding,Neuromorphic engineering,Electronic engineering,Feature extraction,Unsupervised learning,Artificial neural network,Compressed sensing
Conference
3
PageRank 
References 
Authors
0.40
2
2
Name
Order
Citations
PageRank
Shimeng Yu131.07
Yu Cao232929.78