Name
Abstract | ||
|---|---|---|
In modern computation routines, matrix operations are broadly used in many scientific realms, ranging from high performance supercomputers to resource constrained embedded devices. Previous studies have revealed that the computation efficiency of matrix operations is significantly determined by the data accesses behavior of the computation platform. This paper introduces an integrated multicore system, including software stacks and hardware modules that can accelerate matrix operations and reduce data access overhead. With the proposed hardware module, the performance of our multicore embedded platform can improve up to 24.09%. Besides the hardware design, we also develop a framework that can facilitate the prototyping of embedded system designs, including functional verification of hardware modules as well as co-simulation with high level OpenCL language. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/NBiS.2015.50 | NBiS |
Keywords | Field | DocType |
matrix operations, throughput processor, design framework, FPGA, OpenCL | Computer architecture,Functional verification,Computer science,Field-programmable gate array,Software,Throughput,Multi-core processor,Data access,Matrix multiplication,Computation | Conference |
ISSN | Citations | PageRank |
2157-0418 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ping-Ju Wu | 1 | 0 | 0.34 |
| Chien-Yu Lin | 2 | 0 | 0.34 |
| Bo-Cheng Charles Lai | 3 | 177 | 19.25 |