Name
Title | ||
|---|---|---|
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform |
Abstract | ||
|---|---|---|
Three-dimensional (3-D) integration promises continuous systemlevel functional scaling beyond the traditional 2-D device-level geometric scaling. It allows stacking memory dies on top of a logic die using through-silicon vias (TSVs) to realize high bandwidth by deploying the vertical connections between functional blocks. In this paper, we present a design strategy using ESL virtual platform to explore 3-D memory architecture for a heterogeneous multi-core system. Based on the virtual platform, designers can rapidly obtain the 3-D stacking interface for better system performance, energy efficiency, and TSV utilization. A feasible stacking architecture and memory interface which meets the design constraints and performance requirements has been evaluated for the target system. Real multimedia H.264 decoding experiments show that the stacking system can achieve about 30% performance improvement and 20% energy saving, compared to the original 2-D system. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLDI-DAT.2013.6533815 | VLSI-DAT |
Field | DocType | ISSN |
Design strategy,System on a chip,Efficient energy use,Computer science,Electronic engineering,Three-dimensional integrated circuit,Systems architecture,Memory architecture,Embedded system,Performance improvement,Stacking | Conference | 2474-2724 |
ISBN | Citations | PageRank |
978-1-4673-4435-7 | 0 | 0.34 |
References | Authors | |
5 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsien-Ching Hsieh | 1 | 5 | 2.55 |
| Shr-Je Lin | 2 | 0 | 0.34 |
| Chun-nan Liu | 3 | 33 | 7.24 |
| Jen-Chieh Yeh | 4 | 223 | 21.72 |
| Shing-Wu Tung | 5 | 33 | 6.60 |
| Ding-Ming Kwai | 6 | 521 | 46.85 |