Name
Abstract | ||
|---|---|---|
The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction. In this paper, we develop the first cycle-level full-system simulation framework for CPU-GPU integration with detailed memory models. With the simulation framework, we analyze the communication cost between the CPU and GPU for GPU workloads, and perform memory system characterization running both applications concurrently. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSI-DAT.2014.6834872 | VLSI-DAT |
Field | DocType | Citations |
Computer architecture,Central processing unit,Uniform memory access,Memory bandwidth,Shared memory,Cache,Computer science,Real-time computing,Flat memory model,CPU shielding,Microarchitecture | Conference | 2 |
PageRank | References | Authors |
0.40 | 6 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Han Wang | 1 | 2 | 0.40 |
| Gen-Hong Liu | 2 | 2 | 0.40 |
| Jen-Chieh Yeh | 3 | 2 | 0.40 |
| Tse-Min Chen | 4 | 2 | 0.40 |
| Hsu-Yao Huang | 5 | 2 | 0.40 |
| Chia-Lin Yang | 6 | 1033 | 76.39 |
| Shih-Lien Liu | 7 | 2 | 0.40 |
| James Greensky | 8 | 29 | 2.52 |