Name
Abstract | ||
|---|---|---|
Even though three-dimensional integrated circuits (3-D ICs) with through silicon vias (TSVs) potentially provide modern electronic devices with various advantages, current commercial tools do not realize their layout as a whole, but one by one in a stack of dies. The capability of inter-die co-optimization remains largely restricted. This is, in part, due to that the tools draw heavily on 2-D IC's design and implementation styles. Inter-die co-optimization is imperative for 3-D ICs where timing, power, and area are simultaneously considered. In this paper, we show how to enable inter-die co-optimization with adaptive buffering. Empirical results indicate that the proposed scheme eliminates iterative routines, which can help hasten the pace of realizing 3-D integration. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLDI-DAT.2013.6533885 | VLSI-DAT |
Keywords | Field | DocType |
electronic design automation (EDA), inter-die co-optimization, three-dimensional integrated circuit (3-D IC), through-silicon via (TSV) | Integrated circuit layout,Computer science,IC layout editor,Electronic engineering,Electronics,Integrated circuit design,Electronic design automation,Three-dimensional integrated circuit,Physical design,Integrated circuit,Embedded system | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-4673-4435-7 | 0 |
PageRank | References | Authors |
0.34 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chang-Tzu Lin | 1 | 44 | 7.43 |
| Tsu-Wei Tseng | 2 | 143 | 9.34 |
| Yung-Fa Chou | 3 | 244 | 23.76 |
| Chia-Hsin Lee | 4 | 24 | 5.29 |
| Ding-Ming Kwai | 5 | 521 | 46.85 |