Name
Title | ||
|---|---|---|
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array |
Abstract | ||
|---|---|---|
We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">read</sub>
) and cell Inverter Trip voltage (V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">trip</sub>
) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">read</sub>
and V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">trip</sub>
measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSI-DAT.2012.6212589 | Proceedings of Technical Program of 2012 VLSI Design, Automation and Test |
Keywords | Field | DocType |
all-digital read stability,write margin characterization scheme,CMOS 6T SRAM array,cell read disturb voltage measurement,cell inverter trip voltage measurement,SRAM cell array environment,voltage controlled oscillator,counter based digital read-out,data extraction,statistical analysis,resistor based voltage divider,UMC 1P10M standard performance CMOS technology,Monte Carlo simulation,post-layout simulation,memory size 512 KByte,voltage 10 mV,voltage 640 mV,size 55 nm | Inverter,Monte Carlo method,Computer science,Voltage,Electronic engineering,Static random-access memory,CMOS,Voltage-controlled oscillator,Resistor,Voltage divider | Conference |
ISBN | Citations | PageRank |
978-1-4577-2080-2 | 0 | 0.34 |
References | Authors | |
5 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-Wei Lin | 1 | 12 | 3.66 |
| Ming-Chien Tsai | 2 | 87 | 7.34 |
| Hao-i Yang | 3 | 41 | 6.20 |
| Geng-Cing Lin | 4 | 9 | 2.54 |
| Shao-Cheng Wang | 5 | 43 | 5.63 |
| Ching-Te Chuang | 6 | 465 | 76.52 |
| Shyh-Jye Jou | 7 | 420 | 275.67 |
| Wei Hwang | 8 | 254 | 44.40 |
| Nan-Chun Lien | 9 | 13 | 4.18 |
| Kuen-Di Lee | 10 | 48 | 6.10 |
| Wei-Chiang Shih | 11 | 39 | 4.41 |