Name
Abstract | ||
|---|---|---|
This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSI-DAT.2015.7114502 | VLSI-DAT |
Field | DocType | Citations |
Dram,Microcode,Read-only memory,Control theory,Algorithm design,Test algorithm,Computer science,Real-time computing,Electronic engineering,Built-in self-test,Embedded system | Conference | 3 |
PageRank | References | Authors |
0.40 | 7 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chi-Chun Yang | 1 | 3 | 0.40 |
| Jin-Fu Li | 2 | 662 | 59.17 |
| Yun-Chao Yu | 3 | 3 | 0.40 |
| Kuan-Te Wu | 4 | 4 | 1.11 |
| chihyen lo | 5 | 57 | 8.68 |
| Chao-Hsun Chen | 6 | 3 | 0.73 |
| Jenn-Shiang Lai | 7 | 6 | 1.27 |
| Ding-Ming Kwai | 8 | 521 | 46.85 |
| Yung-Fa Chou | 9 | 244 | 23.76 |