Name
Abstract | ||
|---|---|---|
3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes a Built-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most efficient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSI-DAT.2012.6212621 | VLSI-DAT |
Field | DocType | ISSN |
Spare part,Computer science,Electronic engineering,Memory management,Die (manufacturing),Three-dimensional integrated circuit,Maintenance engineering,Blossom algorithm,Stacking,Embedded system,Built-in self-test | Conference | PENDING |
ISBN | Citations | PageRank |
978-1-4577-2080-2 | 6 | 0.48 |
References | Authors | |
9 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Chuan Chi | 1 | 117 | 8.81 |
| Yung-Fa Chou | 2 | 10 | 2.26 |
| Ding-Ming Kwai | 3 | 18 | 2.72 |
| Yu-Ying Hsiao | 4 | 6 | 0.48 |
| Wu, Cheng-Wen | 5 | 1843 | 170.44 |
| Yu-Tsao Hsing | 6 | 75 | 6.44 |
| liming denq | 7 | 60 | 5.46 |
| Tsung-Hsiang Lin | 8 | 6 | 0.48 |