Name
Abstract | ||
|---|---|---|
This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost “host” test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel “pin electronics” (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a “shadow sampler.” |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ETS.2015.7138756 | 2015 20th IEEE European Test Symposium (ETS) |
Keywords | Field | DocType |
ATE,FPGA,MemoryTest,Multi-GHz | Signal conditioning,Computer science,Field-programmable gate array,Electronic engineering,Pattern synthesis,Electronics,Jitter,Computer hardware,Embedded system | Conference |
ISSN | Citations | PageRank |
1530-1877 | 2 | 0.36 |
References | Authors | |
8 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David C. Keezer | 1 | 68 | 17.00 |
| Te-Hui Chen | 2 | 3 | 1.41 |
| Thomas Moon | 3 | 15 | 3.75 |
| D. T. Stonecypher | 4 | 2 | 0.36 |
| Abhijit Chatterjee | 5 | 1949 | 269.99 |
| Hyun Woo Choi | 6 | 35 | 6.71 |
| Sung-Yeol Kim | 7 | 158 | 16.83 |
| Hosun Yoo | 8 | 8 | 1.51 |