Name
Abstract | ||
|---|---|---|
Power consumption during scan-based test becomes a major concern in modern nanometer technologies. Gating the outputs of scan cells can dramatically reduce the scan shift power. In this paper, we utilize the same gating logic at the outputs of scan cells to reduce the capture power consumption. This is achieved by inserting block enable cells (BECs) into the design to dynamically control the gating logic. During capture the BECs enable the gating logic to block the transitions originated from a subset of scan chains or scan segments propagating to combinational logic in order to reduce capture power. The implementation of the proposed method in test compression environment is also discussed. The experimental results on industrial designs show the significant capture power reduction by using proposed techniques. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ATS.2008.33 | ATS |
Field | DocType | ISSN |
Design for testing,Automatic test pattern generation,Logic gate,Gating,Computer science,Scan chain,Combinational logic,Real-time computing,Electronic engineering,Test compression,Encoding (memory) | Conference | 1081-7735 |
Citations | PageRank | References |
13 | 0.94 | 23 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Janusz Rajski | 2 | 2460 | 201.28 |