Paper Info
Title
Stochastic timing error rate estimation under process and temporal variations
Abstract
Reducing design and operational margin is a key factor that makes fabricated chips competitive in terms of speed and power consumption. On the other hand, a smaller margin involves a higher risk that a timing error occurs in field. This paper proposes a stochastic framework that estimates timing error rate under static process variations and dynamic environmental variations for circuits with and without run-time adaptive speed control. The proposed framework extends the state assignment of the continuous-time Markov process used in the previous work so as to take into account within-die random variation, and speeds up the database construction for the transition rate matrix by combining logic simulation and statistical static timing analysis. This paper also demonstrates that the proposed framework can cope with transistor-by-transistor stochastic aging processes. Experimental results show that the within-die random variation deviates the MTTF with σ of 52%. The CPU time for the transition rate matrix computation is reduced to 1/30.
Year
DOI
Venue
2015
10.1109/TEST.2015.7342404
2015 IEEE International Test Conference (ITC)
Keywords
Field
DocType
stochastic timing error rate estimation,temporal variations,static process variations,dynamic environmental variations,continuous-time Markov process,within-die random variation,logic simulation,statistical static timing analysis,transistor-by-transistor stochastic aging processes,MTTF,CPU time,transition rate matrix computation,run-time adaptive speed control
Mean time between failures,Central processing unit,Random variable,Markov process,Statistical static timing analysis,Computer science,Real-time computing,Logic simulation,Transition rate matrix,Computation
Conference
ISSN
Citations 
PageRank 
1089-3539
4
0.43
References 
Authors
7
4
Name
Order
Citations
PageRank
Shoichi Iizuka140.77
Yutaka Masuda282.56
Masanori Hashimoto346279.39
Takao Onoye432968.21