Name
Abstract | ||
|---|---|---|
The paper presents a novel deterministic built-in self-test (BIST) scheme. The proposed solution seamlessly integrates with on-chip EDT-based decompression logic and takes advantage of two key observations: (1) specified positions of ATPG-produced test cubes are typically clustered within a single or a few scan chains for a small number of successive scan shift cycles, (2) only a small fraction of the specified positions are necessary to detect a fault, and most of the remaining ones have several alternatives that can be obtained by inverting preselected scan slices (all scan cells within a given cycle). The proposed approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed logic BIST scheme and are reported herein. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TEST.2015.7342398 | 2015 IEEE International Test Conference (ITC) |
Keywords | Field | DocType |
deterministic BIST scheme,EDT-compressed test patterns,built-in self-test scheme,on-chip EDT-based decompression logic,ATPG-produced test cubes,successive scan shift cycles,fault detection,preselected scan slices,scan cells,reseeding-based solutions,logic BIST scheme | Small number,Logic gate,System on a chip,Computer science,Algorithm,Real-time computing,Electronic engineering,Compression ratio,Built-in self-test,Cube | Conference |
ISSN | Citations | PageRank |
1089-3539 | 0 | 0.34 |
References | Authors | |
32 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grzegorz Mrugalski | 1 | 501 | 35.90 |
| Janusz Rajski | 2 | 2460 | 201.28 |
| Lukasz Rybak | 3 | 2 | 0.70 |
| Jĕdrzej Solecki | 4 | 28 | 4.07 |
| Jerzy Tyszer | 5 | 838 | 74.98 |