Name
Title | ||
|---|---|---|
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering |
Abstract | ||
|---|---|---|
A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858362 | VLSIC |
Field | DocType | Citations |
Computer science,Filter (signal processing),Electronic engineering,CMOS,Bandwidth (signal processing),Jitter,Low jitter,Phase detector,Data-dependent jitter,Periodic graph (geometry) | Conference | 0 |
PageRank | References | Authors |
0.34 | 2 | 14 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masum Hossain | 1 | 0 | 0.34 |
| E.-Hung Chen | 2 | 0 | 0.34 |
| Reza Navid | 3 | 0 | 0.34 |
| Brian S. Leibowitz | 4 | 0 | 0.34 |
| Chuen-huei Adam Chou | 5 | 9 | 1.46 |
| Simon Li | 6 | 27 | 6.27 |
| Myeong-Jae Park | 7 | 0 | 0.34 |
| Jihong Ren | 8 | 101 | 12.55 |
| Barry Daly | 9 | 27 | 6.64 |
| Bruce Su | 10 | 10 | 1.84 |
| Makarand Shirasgaonkar | 11 | 9 | 1.46 |
| Fred Heaton | 12 | 30 | 6.57 |
| Jared Zerbe | 13 | 48 | 9.04 |
| John C. Eble | 14 | 19 | 5.12 |