Name
Abstract | ||
|---|---|---|
A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858400 | VLSIC |
Field | DocType | Citations |
Comparator,Clock recovery,Computer science,Bathtub curve,Electronic engineering,CMOS,Phase detector,Receiver front end,Power consumption,Bit error rate | Conference | 6 |
PageRank | References | Authors |
0.74 | 3 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takayuki Shibasaki | 1 | 66 | 12.00 |
| Win Chaivipas | 2 | 87 | 9.07 |
| Yanfei Chen | 3 | 7 | 2.62 |
| Yoshiyasu Doi | 4 | 115 | 17.56 |
| Takayuki Hamada | 5 | 63 | 8.34 |
| hideki takauchi | 6 | 7 | 1.11 |
| Toshihiko Mori | 7 | 20 | 6.30 |
| Yoichi Koyanagi | 8 | 68 | 13.60 |
| Hirotaka Tamura | 9 | 204 | 32.19 |