Name
Title | ||
|---|---|---|
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier |
Abstract | ||
|---|---|---|
A hybrid dynamic amplifier is proposed which combines the desirable features of a dynamic amplifier and a class AB amplifier. This technique allows us to achieve a power efficient high resolution pipeline ADC. A proof of concept pipelined ADC in a 0.18 μm CMOS process achieves 74.2 dB SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 mm2. The ADC achieves a FoM of 48 fJ/CS without any form of calibration. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858373 | VLSIC |
Field | DocType | Citations |
Total harmonic distortion,Power efficient,Computer science,Spurious-free dynamic range,Electronic engineering,Cmos process,Proof of concept,Electrical engineering,Calibration,Amplifier | Conference | 2 |
PageRank | References | Authors |
0.48 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hariprasath Venkatram | 1 | 36 | 6.72 |
| Taehwan Oh | 2 | 13 | 4.85 |
| Kazuki Sobue | 3 | 24 | 6.42 |
| Koichi Hamashita | 4 | 85 | 15.02 |
| Un-Ku Moon | 5 | 836 | 140.98 |