Name
Title | ||
|---|---|---|
1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS |
Abstract | ||
|---|---|---|
This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSIC.2012.6243831 | VLSIC |
Field | DocType | ISBN |
Computer science,Latency (engineering),Clock domain crossing,Injection locking,Communication channel,Electronic engineering,CMOS,Chip,Power noise,Jitter | Conference | 978-1-4673-0845-8 |
Citations | PageRank | References |
2 | 0.44 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sang-Hye Chung | 1 | 21 | 4.62 |
| Lee-Sup Kim | 2 | 707 | 98.58 |