Name
Title | ||
|---|---|---|
7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique |
Abstract | ||
|---|---|---|
Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858374 | VLSIC |
Field | DocType | Citations |
Flight dynamics (spacecraft),Exponential function,Computer science,CMOS,Electronic engineering,Laser power scaling,Frequency scaling,Binary search algorithm,Nyquist–Shannon sampling theorem,Computer hardware,Cycles per instruction | Conference | 2 |
PageRank | References | Authors |
0.50 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kentaro Yoshioka | 1 | 54 | 9.04 |
| Ryo Saito | 2 | 2 | 0.84 |
| Takumi Danjo | 3 | 2 | 0.50 |
| Sanroku Tsukamoto | 4 | 109 | 18.09 |
| Hiroki Ishikuro | 5 | 285 | 52.15 |