Name
Title | ||
|---|---|---|
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSIC.2012.6243782 | VLSIC |
Field | DocType | Citations |
Wake,Static noise margin,Access time,Standby power,Computer science,Parallel computing,Electronic engineering,Chip,CMOS,Power gating,Macro | Conference | 13 |
PageRank | References | Authors |
0.79 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takashi Ohsawa | 1 | 13 | 0.79 |
| Hiroki Koike | 2 | 25 | 3.90 |
| Sadahiko Miura | 3 | 79 | 7.86 |
| Hiroaki Honjo | 4 | 90 | 11.43 |
| Keiichi Tokutome | 5 | 14 | 1.41 |
| Ikeda, S. | 6 | 36 | 5.83 |
| Takahiro Hanyu | 7 | 441 | 78.58 |
| Hideo Ohno | 8 | 13 | 0.79 |
| Tetsuo Endoh | 9 | 155 | 35.26 |