Name
Abstract | ||
|---|---|---|
Modern operating systems avoid duplication of code and data when they are mapped by multiple processes by sharing physical memory through mechanisms like copy-on-write. Nonetheless, a separate copy of the virtual address translation structures, such as page tables, are still maintained for each process, even if they are identical. This duplication can lead to inefficiencies in the address translation process and interference within the memory hierarchy. In this paper, we show that on Android platforms, sharing address translation structures, specifically, page tables and TLB entries, for shared libraries can improve performance. For example, at a low level, sharing address translation structures reduces the cost of fork by more than half by reducing page table construction overheads. At a higher level, application launch and IPC are faster due to page fault elimination coupled with better cache and TLB performance when context switching. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2901318.2901327 | EuroSys |
Field | DocType | Citations |
Memory hierarchy,Cache,Computer science,Page table,Page address register,Virtual address space,Real-time computing,Page fault,Translation lookaside buffer,Operating system,Context switch | Conference | 5 |
PageRank | References | Authors |
0.42 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaowan Dong | 1 | 6 | 1.10 |
| Sandhya Dwarkadas | 2 | 3504 | 257.31 |
| Alan L. Cox | 3 | 2635 | 223.67 |