Name
Abstract | ||
|---|---|---|
We present the principles of operation and functioning of a CAD software tool for the automated realization of high performance integer arithmetic circuits targeting Xilinx Field Programmable Gate Arrays (FPGAs). The key ideas behind the improvement of circuit performance are optimal usage of the hardware primitives available on the Xilinx FPGA platform, as well as regular, careful and constrained placement of the circuit building blocks on the FPGA fabric. The bit -- sliced architectures of our proposed designs allow us to automatically generate synthesizable, platform -- specific structural Hardware Description Language (HDL) code for the proposed circuits, as well as the placement constraint files needed to control the placement of the design on the given FPGA fabric. Compared against circuits implemented using existing approaches and those automatically generated using existing CAD tools, our automatically generated implementations demonstrate significant speed improvement. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/DSD.2015.18 | Euromicro Symposium on Digital Systems Design |
Keywords | Field | DocType |
Carry chain, Look-Up Table, design automation, FPGA, primitive instantiation, placement | Lookup table,Digital signal processing,Adder,Computer science,Computer Aided Design,Parallel computing,Field-programmable gate array,Electronic design automation,Reconfigurable computing,Embedded system,Hardware description language | Conference |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayan Palchaudhuri | 1 | 11 | 7.67 |
| Rajat Subhra Chakraborty | 2 | 1029 | 81.56 |
| Durga Prasad Sahoo | 3 | 52 | 8.39 |