Name
Title | ||
|---|---|---|
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores. |
Abstract | ||
|---|---|---|
This paper proposes a new network-on-chip (NoC)-reused test access mechanism (TAM) for testing multiple identical cores. It can test multiple cores concurrently and identify faulty cores to derate the chip by excluding the core. In order to minimize the test time, the TAM utilizes the majority value of test response data. All of the cores can thereby be tested in parallel and test costs (in both t... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCAD.2015.2481872 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Multicore processing,Hardware,Testing,Routing,System-on-chip,Bandwidth,Pins | Single-core,System on a chip,Computer science,Reuse,Parallel computing,Network on a chip,Chip,Real-time computing,Bandwidth (signal processing),Spectrum analyzer,Multi-core processor,Embedded system | Journal |
Volume | Issue | ISSN |
35 | 7 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taewoo Han | 1 | 79 | 8.41 |
| Inhyuk Choi | 2 | 15 | 4.75 |
| Hyunggoy Oh | 3 | 14 | 4.80 |
| Sungho Kang | 4 | 12 | 6.64 |