Name
Title | ||
|---|---|---|
Optimization On Layout Strategy Of Gate-Grounded Nmos For On-Chip Esd Protection In A 65-Nm Cmos Process |
Abstract | ||
|---|---|---|
Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS (ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are designed and fabricated in a 65-nm CMOS process. Direct current (DC), transmission-line-pulsing (TLP), human body model (HBM) and very-fast TLP (VF-TLP) tests are executed to fully characterize performance of fabricated ggNMOS. Test results reveal that an enlarged SESS parameter results in an earlier triggering behavior of ggNMOS, which presents a layout option for subtle adjustable triggering behaviors. Besides, inserted substrate-pick stripes are proved to have a bell-shape influence on the ESD robustness of ggNMOS and this bell-shape influence is valid in TLP, HBM and VF-TLP tests. Moreover, the most ESD-robust ggNMOS optimized under different inserted substrate-pick stripes always achieves a higher HBM level over the traditional ggNMOS at each concerned total device-width. Physical mechanisms of test results will be deeply discussed in this work. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1587/transele.E99.C.590 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
electrostatic discharge (ESD), gate-grounded NMOS (ggNMOS), substrate-pickup stripes, transmission-line-pulsing (TLP) test | NMOS logic,Electronic engineering,Cmos process,Engineering,Electrical engineering | Journal |
Volume | Issue | ISSN |
E99C | 5 | 1745-1353 |
Citations | PageRank | References |
1 | 0.40 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guangyi Lu | 1 | 8 | 5.15 |
| Yuan Wang | 2 | 17 | 13.39 |
| zhang | 3 | 10 | 9.77 |