Name
Abstract | ||
|---|---|---|
This paper describes a design methodology for CMOS silicon photonic interconnect ICs according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the highswing transmitter and high-gain receiver required at the silicon photonic interface becomes much more challenging. In this paper, ... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2504459 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Silicon photonics,Modulation,CMOS integrated circuits,Logic gates,CMOS technology,Optical transmitters,Stress | Transmitter,Inverter,Logic gate,Computer science,Voltage,Electronic engineering,Photodetector,CMOS,Transimpedance amplifier,Silicon photonics,Electrical engineering | Journal |
Volume | Issue | ISSN |
24 | 6 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Woo-Rham Bae | 1 | 40 | 14.93 |
| Gyu-Seob Jeong | 2 | 21 | 9.00 |
| Yoonsoo Kim | 3 | 129 | 19.27 |
| Hankyu Chi | 4 | 1 | 1.38 |
| Deog-Kyoon Jeong | 5 | 626 | 119.05 |