Name
Abstract | ||
|---|---|---|
As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenome... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2016.2532878 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Sensors,Magnetic tunneling,Random access memory,MOS devices,Logic gates,Integrated circuit modeling,Resistance | Monte Carlo method,Logic gate,Computer science,Voltage,Electronic engineering,Process variation,Electronic circuit,Electrical engineering,Scalability,Random access,Gate voltage | Journal |
Volume | Issue | ISSN |
24 | 9 | 1063-8210 |
Citations | PageRank | References |
2 | 0.43 | 15 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sara Choi | 1 | 4 | 2.17 |
| Taehui Na | 2 | 95 | 9.98 |
| Jisu Kim | 3 | 211 | 28.11 |
| Jung-Pill Kim | 4 | 101 | 12.78 |
| Seung-Hyuk Kang | 5 | 62 | 9.65 |
| Seong-ook Jung | 6 | 332 | 53.74 |