Title
PDS: pseudo-differential sensing scheme for STT-MRAM.
Abstract
STT-MRAM has been considered as one of the most promising nonvolatile memory candidates in the next-generation of computer architecture. However, the read reliability and dynamic write power concerns greatly hinder its practical application. In this paper, we propose a synergistic solution, namely pseudo-differential sensing (PDS), to jointly address these two concerns. Three techniques, including cell cluster, asymmetric sensing amplifier (ASA) and self-error-detection-correction (SEDC), are proposed to implement the PDS concept. Our experimental results show that the PDS scheme with the 3T3MTJ cell cluster can reduce the area (~21.7%) and write power (~25.6%) of the differential sensing (DS) scheme while improve the read reliability (read margin, ~35.6%) of the typical sensing (TS) scheme for a 16 Mbit cache. Furthermore, the PDS scheme with the 1T3MTJ cell cluster can outperform both the TS and DS schemes in terms of area (~40.0%, ~66.1%), read latency (~16.6%, ~32.1%), read power (~16.7%, ~37.1%), write latency (~5.4%, 16.3%) and write power (~18.6%, ~43.4%).
Year
DOI
Venue
2016
10.1145/2897937.2898058
DAC
Keywords
Field
DocType
STT-MRAM, Asymmetric sensing, Reliability, Write power, Error detection and correction
Latency (engineering),Computer science,Cache,Magnetoresistive random-access memory,Electronic engineering,Error detection and correction,Non-volatile memory,Computer hardware,Cell cluster,Megabit,Amplifier
Conference
Citations 
PageRank 
References 
1
0.35
14
Authors
7
Name
Order
Citations
PageRank
Wang Kang116127.54
Tingting Pang261.47
Bi Wu3176.61
Weifeng Lv430043.72
Youguang Zhang57714.74
Guangyu Sun61920111.55
Weisheng Zhao7730105.43