Name
Title | ||
|---|---|---|
Statistical fault injection for impact-evaluation of timing errors on application performance. |
Abstract | ||
|---|---|---|
This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circuit structure, hence allowing for a significantly more detailed characterization of application performance under scaled frequency / voltage (including supply noise). The model uses gate level timing statistics extracted by dynamic timing analysis from the post place & route netlist of a general-purpose processor to perform instruction-aware fault injections. We employ a 28 nm OpenRISC core as a case study, to demonstrate how statistical fault injection provides a more accurate and realistic analysis of power vs. error performance. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2897937.2898095 | DAC |
Keywords | Field | DocType |
statistical fault injection,impact-evaluation,application performance characterization,gate level timing error modeling,high-level instruction set simulation,circuit structure,gate level timing statistics,dynamic timing analysis,post place & route netlist,general-purpose processor,instruction-aware fault injections,OpenRISC core,power performance,frequency scaling,voltage scaling,size 28 nm | Netlist,Logic gate,OpenRISC,Computer science,Voltage,High-level synthesis,Real-time computing,Electronic engineering,Static timing analysis,Benchmark (computing),Fault injection | Conference |
ISBN | Citations | PageRank |
978-1-4673-8730-9 | 0 | 0.34 |
References | Authors | |
13 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeremy Constantin | 1 | 40 | 4.86 |
| A. Burg | 2 | 1426 | 126.54 |
| Zheng Wang | 3 | 0 | 0.34 |
| Anupam Chattopadhyay | 4 | 63 | 15.06 |
| Georgios Karakonstantis | 5 | 317 | 37.08 |