Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference | 2 | 0.38 | 2019 |
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. | 5 | 0.55 | 2017 |
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems | 2 | 0.46 | 2017 |
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. | 0 | 0.34 | 2016 |
Statistical fault injection for impact-evaluation of timing errors on application performance. | 0 | 0.34 | 2016 |
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment | 15 | 0.75 | 2015 |
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms | 1 | 0.38 | 2013 |
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. | 0 | 0.34 | 2012 |
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. | 3 | 0.37 | 2012 |
Low-power processor architecture exploration for online biomedical signal analysis. | 12 | 0.96 | 2012 |