Name
Abstract | ||
|---|---|---|
Traditional datapath synthesis for standard-cell designs go through extraction of arithmetic operations from the high-level description, high-level synthesis, and netlist generation. In this paper, we take a fresh look at applying high-level synthesis methodologies in logic synthesis. We present a DAG-Aware synthesis technique for datapaths synthesis which is implemented using And-Inv-Graphs. Our approach targets area minimization. The proposed algorithm includes identifying vector multiplexers, searching for common specification logic, and reallocating multiplexers in the Boolean network. We propose an algorithm to identify common specification logic by using subgraph isomorphism. Experimental results show that our technique can provide over 10% area reduction beyond the traditional design flow. The proposed algorithm is tested on industry designs and academic benchmark suits using IBM 14nm technology. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2897937.2898000 | DAC |
Keywords | Field | DocType |
Logic synthesis, AIGs, datapaths, resource sharing | Logic synthesis,Boolean circuit,Datapath,Computer science,Logic optimization,Parallel computing,Combinational logic,Electronic engineering,Logic family,Register-transfer level,Hardware description language | Conference |
Citations | PageRank | References |
1 | 0.36 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunxi Yu | 1 | 98 | 9.64 |
| Maciej J. Ciesielski | 2 | 629 | 74.80 |
| Mihir R. Choudhury | 3 | 184 | 15.40 |
| Andrew Sullivan | 4 | 3 | 1.45 |