Name
Abstract | ||
|---|---|---|
This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A study is performed to observe variational gate output waveforms, and a technique is presented to store the waveforms in a memory efficient manner with minimal accuracy impact. The presented technique is validated over a set of 14 nanometer designs, and has enabled the usage of current source models in our industrial statistical timing analysis flow. Results demonstrate slack accuracy improvements of up to 17 picoseconds with a 1.15X run-time overhead and 1.1 gigabytes per million-gates memory overhead in comparison to an existing flow. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2897937.2898068 | DAC |
Keywords | Field | DocType |
Statistical timing, current source models, variability | Delay calculation,Logic gate,Statistical static timing analysis,Current source,Computer science,Microprocessor,Waveform,Electronic engineering,Real-time computing,Memory management,Static timing analysis | Conference |
Citations | PageRank | References |
2 | 0.37 | 14 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Debjit Sinha | 1 | 147 | 18.25 |
| Vladimir Zolotov | 2 | 1367 | 109.07 |
| Sheshashayee K. Raghunathan | 3 | 2 | 0.71 |
| Michael Wood | 4 | 16 | 2.98 |
| Kerim Kalafala | 5 | 2 | 0.37 |