Title | ||
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Compact Associative Memory For Aer Spike Decoding In Fpga-Based Evolvable Snn Emulation |
Abstract | ||
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A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking Neural Network (SNN) emulators is introduced. The proposed scheme is a modified associative memory based on an efficient use of BRAM, supporting connectivity upgrade in real-time for hardware implementations of evolutionary networks. After analysing the different options and selecting the most efficient one, a prototype example based on FPGA is provided together with a novel hashing technique to demonstrate a compact on-chip solution for implementing inter-chip connectivity in SNN. |
Year | DOI | Venue |
---|---|---|
2016 | 10.1007/978-3-319-44778-0_47 | ARTIFICIAL NEURAL NETWORKS AND MACHINE LEARNING - ICANN 2016, PT I |
Keywords | Field | DocType |
Associative memory, SNN, AER, Digital neuromorphic systems, Evolvable connections | Content-addressable memory,Cognitive science,Computer science,Artificial intelligence,Spiking neural network,Computer architecture,Hardware implementations,Field-programmable gate array,Upgrade,Emulation,Hash function,Decoding methods,Machine learning | Conference |
Volume | ISSN | Citations |
9886 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 3 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
mireya zapata | 1 | 9 | 3.45 |
Jordi Madrenas | 2 | 150 | 27.87 |