Name
Abstract | ||
|---|---|---|
LZW algorithm is one of the most famous dictionary-based compression and decompression algorithms. The main contribution of this paper is to present a hardware LZW decompression algorithm and to implement it in an FPGA. The experimental results show that one proposed module on Virtex-7 family FPGA XC7VX485T-2 runs up to 2.16 times faster than sequential LZW decompression on a single CPU, where the frequency of FPGA is 301.02MHz. Since the proposed module is compactly designed and uses a few resources of the FPGA, we have succeeded to implement 150 identical modules which works in parallel on the FPGA, where the frequency of FPGA is 245.4MHz. In other words, our implementation runs up to 264 times faster than a sequential implementation on a single CPU. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/IPDPSW.2016.33 | 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | Field | DocType |
LZW decompression,FPGA,block RAMs | Decompression,Block ram,Algorithm design,Computer science,Parallel computing,Field-programmable gate array,Image coding,Hardware algorithm,Computer hardware,Data compression | Conference |
ISSN | ISBN | Citations |
2164-7062 | 978-1-5090-3683-7 | 3 |
PageRank | References | Authors |
0.45 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xin Zhou | 1 | 17 | 5.43 |
| Yasuaki Ito | 2 | 511 | 60.47 |
| Koji Nakano | 3 | 1165 | 118.13 |