Paper Info
Title
On How to Improve FPGA-Based Systems Design Productivity via SDAccel
Abstract
Custom hardware accelerators are widely used to improve the performance of software applications in terms of execution times and to reduce energy consumption. However the realization of an hardware accelerator and its integration in the final system is a difficult and error prone task. For this reason, both Industry and Academy are continuously developing Computer Aided Design (CAD) tools to assist the designer in the development process. Even if many of the steps have been nowadays automated, system integration and SW/HW interfaces definition and drivers generation are still almost completely manual tasks. The last tool released by Xilinx, however, aims at improving the hardware design experience by leveraging the OpenCL standard to enhance the overall productivity and to enable code portability. This paper provides an overview of the SDAccel potentiality comparing its design flow with other methodologies using two case studies from the Bioinformatics field: brain network and protein folding analysis.
Year
DOI
Venue
2016
10.1109/IPDPSW.2016.171
2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Keywords
Field
DocType
code portability,OpenCL standard,Xilinx,drivers generation,SW/HW interfaces,system integration,CAD tools,computer aided design,energy consumption,software applications,custom hardware accelerators,SDAccel,FPGA-based systems design productivity
Hardware compatibility list,Computer science,Parallel computing,Systems design,Design flow,Hardware acceleration,Software portability,Open source hardware,Distributed computing,Hardware architecture,System integration,Embedded system
Conference
ISSN
ISBN
Citations 
2164-7062
978-1-5090-3683-7
13
PageRank 
References 
Authors
0.91
8
6
Name
Order
Citations
PageRank
Giulia Guidi1131.25
Enrico Reggiani2163.35
Lorenzo Di Tucci3183.48
Gianluca Durelli4307.13
Michaela Blott531525.60
Marco D. Santambrogio677191.15