Name
Abstract | ||
|---|---|---|
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based systems that allows to achieve high quality results in terms of overall application execution time. The proposed algorithm exploits the notion of resource efficient task implementations in order to reduce the overhead incurred by partial dynamic reconfiguration and increase the number of concurrent tasks that can be hosted on the reconfigurable logic as hardware accelerators. We evaluate a fast deterministic version of the scheduler that is able to find good quality solutions in a small amount of time and a randomized version of the approach that can be executed multiple times to improve the final result. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/IPDPSW.2016.176 | 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | Field | DocType |
Scheduling,Field Programmable Gate Array,Partial Dynamic Reconfiguration,System on Chip,Reconfigurable Architectures | System on a chip,Scheduling (computing),Computer science,Parallel computing,Field-programmable gate array,Exploit,Implementation,Software,Schedule,Control reconfiguration,Distributed computing | Conference |
ISSN | ISBN | Citations |
2164-7062 | 978-1-5090-3683-7 | 6 |
PageRank | References | Authors |
0.53 | 10 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Purgato | 1 | 7 | 0.88 |
| Davide Tantillo | 2 | 6 | 0.53 |
| Marco Rabozzi | 3 | 41 | 7.58 |
| D. Sciuto | 4 | 1720 | 176.61 |
| Marco D. Santambrogio | 5 | 771 | 91.15 |