Title
Evaluation of an Analog Accelerator for Linear Algebra.
Abstract
Due to the end of supply voltage scaling and the increasing percentage of dark silicon in modern integrated circuits, researchers are looking for new scalable ways to get useful computation from existing silicon technology. In this paper we present a reconfigurable analog accelerator for solving systems of linear equations. Commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty in programming are all compensated for using methods we discuss. Based on a prototyped analog accelerator chip we compare the performance and energy consumption of the analog solver against an efficient digital algorithm running on a CPU, and find that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design. Due to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint. Finally, we conclude that problem classes outside of systems of linear equations may hold more promise for analog acceleration.
Year
DOI
Venue
2016
10.1109/ISCA.2016.56
ISCA
Keywords
DocType
ISSN
accelerator architectures, analog-digital integrated circuits, analog computers, linear algebra
Conference
1063-6897
ISBN
Citations 
PageRank 
978-1-4673-8948-8
3
0.41
References 
Authors
19
5
Name
Order
Citations
PageRank
Yipeng Huang1232.82
Ning Guo2146.52
Mingoo Seok360180.71
Yannis P. Tsividis433373.63
Simha Sethumadhavan592554.24