Name
Title | ||
|---|---|---|
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission |
Abstract | ||
|---|---|---|
An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction corresponding to the "context" of the data stream. Through the evaluation of intra-chip data transmission in a general-purpose 32-bit microprocessor, it is demonstrated that the proposed scheme performs 95.9% error reduction with 2-times better data transfer efficiency and 94.2% error reduction with 4-times better data transfer efficiency compared with a conventional error correction scheme. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISMVL.2016.42 | 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) |
Keywords | Field | DocType |
intelligent information processing,deep learning,recurrent neural network,context-based error correction | Data mining,Data transmission,Computer science,Data stream,Context based,Microprocessor,Recurrent neural network,Error detection and correction,Chip,Artificial intelligence,Deep learning | Conference |
ISSN | ISBN | Citations |
0195-623X | 978-1-4673-9490-1 | 0 |
PageRank | References | Authors |
0.34 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoto Sugaya | 1 | 0 | 0.34 |
| Masanori Natsui | 2 | 80 | 15.10 |
| Takahiro Hanyu | 3 | 441 | 78.58 |