Name
Abstract | ||
|---|---|---|
In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ICICDT.2016.7542076 | 2016 International Conference on IC Design and Technology (ICICDT) |
Keywords | Field | DocType |
Advanced Encryption Standards,AES,Low-Power,Low-Energy,IoT | 32-bit,Clock gating,Datapath,Shift register,Computer science,Real-time computing,Encryption,Throughput,Energy consumption,Microarchitecture,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-0321-1 | 2 | 0.39 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Duy-Hieu Bui | 1 | 13 | 2.83 |
| Diego Puschini | 2 | 71 | 10.76 |
| Simone Bacles-Min | 3 | 2 | 0.39 |
| Edith Beigne | 4 | 536 | 52.54 |
| Xuan-Tu Tran | 5 | 91 | 11.87 |