| System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars | 1 | 0.41 | 2022 |
| Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications | 0 | 0.34 | 2022 |
| Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications | 0 | 0.34 | 2021 |
| SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency | 1 | 0.37 | 2020 |
| Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture | 2 | 0.39 | 2019 |
| Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning | 0 | 0.34 | 2019 |
| Spiking Neural Networks Hardware Implementations and Challenges: A Survey | 9 | 0.49 | 2019 |
| A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing | 2 | 0.40 | 2019 |
| A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS | 1 | 0.35 | 2019 |
| Fine-grain Back Biasing for the Design of Energy-Quality Scalable Operators | 0 | 0.34 | 2019 |
| 14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques | 0 | 0.34 | 2019 |
| Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee | 0 | 0.34 | 2018 |
| Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges | 0 | 0.34 | 2018 |
| Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. | 0 | 0.34 | 2018 |
| A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. | 0 | 0.34 | 2018 |
| Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. | 0 | 0.34 | 2018 |
| A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing | 0 | 0.34 | 2018 |
| FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience. | 0 | 0.34 | 2018 |
| Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. | 5 | 0.55 | 2017 |
| Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC | 1 | 0.63 | 2017 |
| Session 20 overview: Digital voltage regulators and low-power techniques. | 0 | 0.34 | 2017 |
| Session 26 overview: Processor-power management and clocking. | 0 | 0.34 | 2017 |
| Architecture exploration of a fixed point computation unit using precise timing spiking neurons | 0 | 0.34 | 2017 |
| A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. | 2 | 0.47 | 2017 |
| A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. | 2 | 0.40 | 2017 |
| AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. | 8 | 0.67 | 2017 |
| High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. | 2 | 0.53 | 2017 |
| A methodology for the design of dynamic accuracy operators by runtime back bias. | 1 | 0.38 | 2017 |
| Session 8 overview: Digital PLLs and security circuits | 0 | 0.34 | 2017 |
| Adaptive Architectures, Circuits And Technology Solutions For Future Iot Systems | 0 | 0.34 | 2017 |
| Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference | 0 | 0.34 | 2016 |
| 8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links | 10 | 0.78 | 2016 |
| Tracking BTI and HCI effects at circuit-level in adaptive systems | 0 | 0.34 | 2016 |
| Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications | 2 | 0.39 | 2016 |
| UTBB FDSOI technology flexibility for ultra low power internet-of-things applications | 1 | 0.39 | 2015 |
| A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking | 5 | 0.49 | 2015 |
| Unified Power Format (UPF) methodology in a vendor independent flow | 1 | 0.44 | 2015 |
| Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit | 0 | 0.34 | 2015 |
| A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems | 2 | 0.38 | 2015 |
| Radiative Effects on MRAM-Based Non-Volatile Elementary Structures | 0 | 0.34 | 2015 |
| Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing | 0 | 0.34 | 2015 |
| Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller | 0 | 0.34 | 2015 |
| Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology | 3 | 0.45 | 2015 |
| Fine-Grain Dvfs And Avfs Techniques For Complex Soc Design: An Overview Of Architectural Solutions Through Technology Nodes | 0 | 0.34 | 2015 |
| Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor | 0 | 0.34 | 2015 |
| Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures | 2 | 0.38 | 2014 |
| A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC. | 0 | 0.34 | 2014 |
| 27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking | 0 | 0.34 | 2014 |
| FIFO-level-based power management and its application to an H.264 encoder | 0 | 0.34 | 2014 |
| Power management through DVFS and dynamic body biasing in FD-SOI circuits | 5 | 0.58 | 2014 |
