Name
Abstract | ||
|---|---|---|
Over the last years, methodologies based on Quasi-Monte Carlo techniques have often been used to estimate the impact of variability on failure probabilities. Such techniques have been employed largely on planar CMOS designs of older technologies. This paper examines the boundaries of such an approach on netlists with heavily scaled CMOS FinFET devices for testing with 6-sigma design margins. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ICICDT.2016.7542044 | 2016 International Conference on IC Design and Technology (ICICDT) |
Keywords | Field | DocType |
Failure Probability,Quasi-Monte Carlo,6-sigma | Quasi-Monte Carlo method,Real-time computing,Electronic engineering,CMOS,Planar,Engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-0321-1 | 1 | 0.37 |
References | Authors | |
6 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michail Noltsis | 1 | 2 | 1.74 |
| Pieter Weckx | 2 | 52 | 16.96 |
| Dimitrios Rodopoulos | 3 | 56 | 9.74 |
| Francky Catthoor | 4 | 3932 | 423.30 |
| Dimitrios Soudris | 5 | 243 | 48.41 |