Name
Abstract | ||
|---|---|---|
Approximate computing techniques based on Voltage Over-Scaling (VOS) can provide quadratic improvements in power efficiency. However, voltage scaling is limited by the inherent fault-tolerance of an application, thus preventing VOS schemes from realizing their full potential. To gain further power efficiency a reduction of the error rate experienced in a given voltage level is required. We propose Lazy Pipelines, a micro-architectural technique that utilizes vacant cycles in a VOS functional unit to extend execution and reduce the error rate. |
Year | Venue | Keywords |
|---|---|---|
2016 | DATE | approximate computing, power efficiency, micro-architecture |
Field | DocType | ISSN |
Electrical efficiency,Pipeline transport,Computer science,Voltage,Word error rate,Parallel computing,Quadratic equation,Real-time computing,Scaling,Bit error rate,Microarchitecture | Conference | 1530-1591 |
Citations | PageRank | References |
3 | 0.43 | 7 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. Tziantzioulis | 1 | 17 | 1.75 |
| A. M. Gok | 2 | 14 | 1.36 |
| Faisal, S.M. | 3 | 21 | 2.19 |
| Nikolaos Hardavellas | 4 | 226 | 20.82 |
| Seda Öǧrenci Memik | 5 | 488 | 42.57 |
| Srinivasan Parthasarathy | 6 | 4666 | 375.76 |