Paper Info
Title
Fault Tolerant Non-Volatile spintronic flip-flop
Abstract
With technology down scaling, static power has become one of the biggest challenges in a System-On-Chip. Normally-off computing using non-volatile sequential elements is a promising solution to address this challenge. Recently, many non-volatile shadow flip-flop architectures have been introduced in which Magnetic Tunnel Junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. So, without effective defect and fault tolerance for non-volatile flip-flops, the manufacturing yield will be severely affected. In this paper, we propose a Fault Tolerant Non-Volatile Latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. Simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with considerably lower overhead than traditional approaches.
Year
Venue
Keywords
2016
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
technology down scaling,static power,normally-off computing,nonvolatile sequential elements,nonvolatile shadow flip-flop architectures,magnetic tunnel junction cells,MTJ cells,backup storing elements,defect tolerance,fault tolerance,manufacturing yield,fault tolerant nonvolatile latch design,FTNV-L design
Field
DocType
ISSN
Computer science,Electronic engineering,CMOS,Non-volatile memory,Fault tolerance,Tunnel magnetoresistance,Flip-flop,Scaling,Fabrication,Backup,Embedded system
Conference
1530-1591
Citations 
PageRank 
References 
1
0.36
3
Authors
3
Name
Order
Citations
PageRank
Rajendra Bishnoi113219.64
Fabian Oboril228826.71
Mehdi B. Tahoori31537163.44