Paper Info
Title
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.
Abstract
Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.
Year
DOI
Venue
2016
10.1145/2902961.2903022
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
Spin Orbit Torque, multi-port non-volatile memory
Architecture,Leakage (electronics),Shared memory,Computer science,Latency (engineering),Register file,Electronic engineering,Data integrity,Computer hardware,Memory architecture,Scalability,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-5090-2979-2
1
0.35
References 
Authors
10
3
Name
Order
Citations
PageRank
Rajendra Bishnoi113219.64
Fabian Oboril228826.71
Mehdi B. Tahoori31537163.44