Paper Info
Title
Evaluation Of 3-D Stencil Codes On The Intel Xeon Phi Coprocessor
Abstract
Accelerators like the Intel Xeon Phi aim to fulfill the computational requirements of modern applications, including stencil computations. Stencils are finite-difference algorithms used in many scientific and engineering applications for solving large-scale and high-dimension partial differential equations. However, programmability on such massively parallel architectures is still a challenge for inexperienced developers.This paper provides the evaluation of the Intel Xeon Phi (Knights Corner) for 3-D Stencil Codes using different optimization strategies. Our evaluation is based on three kernels that are widely applied to simulate heat, acoustic diffusion as well as isotropic seismic wave equations. Our experimental results yield performance gains over 25x when compared to high-level sequential implementations (e.g., Matlab). Energy measurements show a similar trend to that of performance. Vectorization is the key strategy from our results, from both performance and energy points of view.In addition, we propose a set of tips to optimize stencil codes based on a C/C++ OpenMP implementation. We guide developers in maximizing the benefits of hardware-software co-design for computing 3-D stencil codes running on the this architecture.
Year
DOI
Venue
2015
10.3233/978-1-61499-621-7-197
PARALLEL COMPUTING: ON THE ROAD TO EXASCALE
Keywords
Field
DocType
3-D stencil codes, Xeon Phi, performance optimizations, 3-D finite difference
Computer science,Parallel computing,Stencil code,Intel xeon phi coprocessor
Conference
Volume
ISSN
Citations 
27
0927-5452
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Mario Hernández120.73
Juan Manuel Cebrian22410.19
José M. Cecilia316622.28
jose m garcia410513.66