| Compiler-Assisted Compaction/Restoration of SIMD Instructions | 0 | 0.34 | 2022 |
| Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations | 0 | 0.34 | 2021 |
| Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86 | 0 | 0.34 | 2020 |
| High-throughput fuzzy clustering on heterogeneous architectures | 0 | 0.34 | 2020 |
| Using Arm’s scalable vector extension on stencil codes | 4 | 0.52 | 2020 |
| Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions | 0 | 0.34 | 2020 |
| Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies | 0 | 0.34 | 2020 |
| Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance | 0 | 0.34 | 2020 |
| Boosting Store Buffer Efficiency with Store-Prefetch Bursts | 0 | 0.34 | 2020 |
| Scalability analysis of AVX-512 extensions | 0 | 0.34 | 2020 |
| POSTER: An Optimized Predication Execution for SIMD Extensions | 0 | 0.34 | 2019 |
| Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. | 0 | 0.34 | 2018 |
| Stencil codes on a vector length agnostic architecture | 1 | 0.35 | 2018 |
| A dedicated private-shared cache design for scalable multiprocessors. | 1 | 0.39 | 2017 |
| Code modernization strategies to 3-D Stencil-based applications on Intel Xeon Phi: KNC and KNL. | 1 | 0.35 | 2017 |
| Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network | 0 | 0.34 | 2016 |
| V-PFORDelta: Data Compression for Energy Efficient Computation of Time Series. | 2 | 0.38 | 2015 |
| Evaluation Of 3-D Stencil Codes On The Intel Xeon Phi Coprocessor | 0 | 0.34 | 2015 |
| Evaluation of the 3-D finite difference implementation of the acoustic diffusion equation model on massively parallel architectures | 2 | 0.39 | 2015 |
| Soft-error mitigation by means of decoupled transactional memory threads | 1 | 0.35 | 2015 |
| ParVec: vectorizing the PARSEC benchmark suite | 4 | 0.49 | 2015 |
| Early Experiences with Separate Caches for Private and Shared Data | 2 | 0.41 | 2015 |
| Managing power constraints in a single-core scenario through power tokens | 0 | 0.34 | 2014 |
| Toward energy efficiency in heterogeneous processors: findings on virtual screening methods | 1 | 0.36 | 2014 |
| Energy-Efficient Sparse Matrix Autotuning with CSX -- A Trade-off Study | 0 | 0.34 | 2013 |
| Modeling the impact of permanent faults in caches | 5 | 0.47 | 2013 |
| Token3D: reducing temperature in 3d die-stacked CMPs through cycle-level power control mechanisms | 0 | 0.34 | 2011 |
| Leakage-efficient design of value predictors through state and non-state preserving techniques | 0 | 0.34 | 2011 |
