Paper Info
Title
Mpi Communication On Mppa Many-Core Noc: Design, Modeling And Performance Issues
Abstract
Keeping up with the performance trend of the last decades cannot be achieved anymore by stepping up the clock speed of processors. The usual strategy is nowadays to use lower frequency and to increase the number of cores, where data communication and memory bandwidth can become the main barrier. In this paper, we introduce an MPI design and its implementation on the MPPA-256 (Multi Purpose Processor Array) processor from Kalray Inc., one of the first worldwide actors in the many-core architecture field. A model was developed to evaluate the communication performance and bottlenecks on MPPA. Our achieved result of 1.2 GB/s, e.g. 75% of peak throughput, for on-chip communication shows that the MPPA is a promising architecture for next-generation HPC systems, with its high performance-to-power ratio and high-bandwidth network-on-chip.
Year
DOI
Venue
2015
10.3233/978-1-61499-621-7-113
PARALLEL COMPUTING: ON THE ROAD TO EXASCALE
Keywords
Field
DocType
Many-core, NUMA, Distributed memory, Network-on-Chip, MPI, Performance modeling, MPPA
Computer architecture,Computer science,Parallel computing,Design modeling
Conference
Volume
ISSN
Citations 
27
0927-5452
0
PageRank 
References 
Authors
0.34
0
5
Name
Order
Citations
PageRank
Minh Quan Ho100.34
Bernard Tourancheau243652.28
Christian Obrecht312611.55
Benoît Dupont de Dinechin419712.60
Jérôme Reybert500.68