Paper Info
Title
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.
Abstract
This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.
Year
DOI
Venue
2016
10.1007/s11432-015-5455-y
SCIENCE CHINA Information Sciences
Keywords
Field
DocType
electrostatic discharge (ESD), power-rail ESD clamp circuit, detection mechanism, transient-noise immunity, false triggering, transmission line pulsing (TLP) test, 静电放电, 电源钳位ESD保护电路, 探测机制, 瞬态噪声免疫力, 误触发, 传输线脉冲测试
Leak,Leakage (electronics),Control theory,Electrostatic discharge,Electronic engineering,Cmos process,Thyristor,Electronic circuit,Mathematics,Clamper,Embedded system,Biasing
Journal
Volume
Issue
ISSN
59
12
1869-1919
Citations 
PageRank 
References 
0
0.34
4
Authors
5
Name
Order
Citations
PageRank
Guangyi Lu185.15
Yuan Wang21713.39
Lizhong Zhang331.23
Jian Cao474.76
zhang5109.77